ASIC EDA Flow Specialist
Share
Job Location:
Monthly Salary:
Posted on:
Vacancies:
Job Summary
Our client is a tech company specializing in the design and development of cutting-edge customized
server hardware solutions optimized for artificial intelligence and machine learning applications.
server hardware solutions optimized for artificial intelligence and machine learning applications.
Their mission is to empower businesses and researchers to accelerate their AI initiatives by
providing them with high-performance scalable and energy-efficient hardware infrastructure.
providing them with high-performance scalable and energy-efficient hardware infrastructure.
As a rapidly growing company at the forefront of AI hardware innovation they are constantly seeking
talented and motivated individuals to join our team. They offer a dynamic and challenging work
environment with opportunities to make a significant impact on the future of AI technology.
Your Mission
As an ASIC EDA Flow Specialist you will be responsible for architecting developing and
maintaining the design flows and infrastructure that power our AI ASIC development. You will
partner closely with RTL verification physical design and CAD engineers to build robust scalable
and efficient EDA environments that accelerate the path from RTL to silicon.
Responsibilities
Develop maintain and optimize ASIC EDA flows across front-end back-end and sign-off
stages from RTL to GDS.
Requirements
Develop and maintain dashboards for EDA tool usage license consumption and
compute/storage monitoring.
talented and motivated individuals to join our team. They offer a dynamic and challenging work
environment with opportunities to make a significant impact on the future of AI technology.
Your Mission
As an ASIC EDA Flow Specialist you will be responsible for architecting developing and
maintaining the design flows and infrastructure that power our AI ASIC development. You will
partner closely with RTL verification physical design and CAD engineers to build robust scalable
and efficient EDA environments that accelerate the path from RTL to silicon.
Your expertise will ensure our teams can innovate faster with best-in-class automation quality of
results and time-to-tape-out.
results and time-to-tape-out.
Responsibilities
Develop maintain and optimize ASIC EDA flows across front-end back-end and sign-off
stages from RTL to GDS.
Manage EDA tool installations updates and license servers (FlexLM RLM SCL) including
license forecasting allocation and vendor coordination.
license forecasting allocation and vendor coordination.
Oversee compute grid and storage infrastructure ensuring optimal job scheduling resource
utilization and uptime for large-scale ASIC builds.
Architect and maintain Git-based infrastructure (GitLab) for design version control CI/CD and
team collaboration.
utilization and uptime for large-scale ASIC builds.
Architect and maintain Git-based infrastructure (GitLab) for design version control CI/CD and
team collaboration.
Manage and support IP vendor tools including evaluation installation and maintenance of
vendor-specific environments (e.g. TSMC ARM Synopsys Cadence).
vendor-specific environments (e.g. TSMC ARM Synopsys Cadence).
Coordinate and track Soft and Hard IP integration within EDA flows managing deliverables
versioning and quality checks.
versioning and quality checks.
Maintain a central IP database with metadata (version PDK constraints verification status) to
streamline reuse across projects.
streamline reuse across projects.
Collaborate with design teams to integrate third-party IPs into custom SoC flows and validate
tool/IP compatibility.
tool/IP compatibility.
Automate repetitive setup tasks (e.g. IP import constraint generation regression setup
reporting) to improve productivity.
reporting) to improve productivity.
Requirements
Ready to Accelerate the Future of AI
If youre passionate about building world-class design flows and enabling engineers to push the
limits of silicon performance they would love to hear from you.
If youre passionate about building world-class design flows and enabling engineers to push the
limits of silicon performance they would love to hear from you.
Develop and maintain dashboards for EDA tool usage license consumption and
compute/storage monitoring.
Document flow methodologies and provide internal training for new engineers.
Profile requirements:
Bachelors or Masters degree in Electrical Engineering Computer Engineering or a related field.
Bachelors or Masters degree in Electrical Engineering Computer Engineering or a related field.
7 years of experience in ASIC/SoC design environment management CAD/EDA flow
development or design infrastructure engineering.
development or design infrastructure engineering.
Strong knowledge of EDA tools (Synopsys Cadence Siemens/Mentor) and their installation
configuration and licensing.
configuration and licensing.
Experience with EDA license servers (FlexLM RLM SCL) and usage optimization.
Proficiency in Tcl Python Yaml and Shell scripting for automation and flow development.
Proficiency in Make CMake or Bazel-based orchestration frameworks for flow and regression
builds.
builds.
Familiarity with compute grid management systems (LSF SLURM Grid Engine) and storage
architecture for large ASIC projects.
architecture for large ASIC projects.
Practical experience with Git and integration into design workflows.
Proficiency in CI/CD automation pipelines or internal build systems.
Solid understanding of RTL-to-GDSII flow timing/power trade-offs and tool interactions.
Strong communication documentation and problem-solving skills.
Strong communication documentation and problem-solving skills.
Exposure to advanced process nodes (7 nm and below) and multi-die design methodologies.
Why join
Work at the intersection of AI and silicon to enable breakthroughs that power the next
generation of intelligent computing.
Join a highly experienced fast-moving team that values technical depth innovation and
hands-on impact.
Build and own EDA methodologies that directly influence silicon performance cost and
scalability.
Enjoy an environment that rewards initiative collaboration and continuous learning.
Competitive compensation growth opportunities and the chance to shape the core
infrastructure behind cutting-edge
generation of intelligent computing.
Join a highly experienced fast-moving team that values technical depth innovation and
hands-on impact.
Build and own EDA methodologies that directly influence silicon performance cost and
scalability.
Enjoy an environment that rewards initiative collaboration and continuous learning.
Competitive compensation growth opportunities and the chance to shape the core
infrastructure behind cutting-edge
Please ignore the salary levels mentioned here: the client is flexible depending on your profile.
Required Experience:
IC
About Company
The Complete Global Talent Acquisition Partner, MBR offers solutions from Executive Search through to highly cost effective Partnership Resourcing models.
