ASIC Design Verification Engineer

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications. You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based testbench development to verification closure. Along with traditional simulation, you will be able to use other approaches like Formal and Emulation to achieve a bug-free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

ASIC Design Verification Engineer Responsibilities:

• Develop functional tests based on verification test plan.
• Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
• Debug, root-cause and resolve functional failures in the design, partnering with the design/arch team.
• Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
  

Minimum Qualifications:

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
• Hands-on experience using constrained-random, coverage driven verification or C/C++ verification.
• Hands-on experience in verifying a IP block using standard DV based techniques.
• Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  

Preferred Qualifications:

• Experience in development of SV/UVM based verification environments from scratch.
• Experience debugging fails to the line of RTL, closing out bug fixes, using Verdi or equivalent debug tools.
• Experience with revision control systems like Mercurial(Hg), Git or SVN.
• Experience working in a CPU/GPU environment.