Solidigm

Detailed responsibility includes but not limit to:Early engagement with NPI process development teams to influence DFM (design for manufacturing) DFA (design for assembly) and proliferate a newly developed HVM recipeCollaborate with NPI engineering in developing new SSD rework techniq

Detailed responsibility includes but not limit to:Early engagement with NPI process development teams to influence DFM (design for manufacturing) DFA (design for assembly) and proliferate a newly developed HVM recipeCollaborate with NPI engineering in developing new SSD rework techniq

Senior Simulator Software EngineerCome join our Data Center Engineering Team and work on one of the most advanced 3D-NAND and SSD technology portfolios in the world. As the global leader in the semiconductor industry Solidigm possesses many industry-leading SSD technologies including

Senior Simulator Software EngineerCome join our Data Center Engineering Team and work on one of the most advanced 3D-NAND and SSD technology portfolios in the world. As the global leader in the semiconductor industry Solidigm possesses many industry-leading SSD technologies including

High Speed Data & IO designKey Responsibilities:Design and develop high-speed IO and data interface circuits including drivers receivers clocking and serialization/deserialization (SerDes) components.Work closely with system architects and RTL designers to define interface requirement

High Speed Data & IO designKey Responsibilities:Design and develop high-speed IO and data interface circuits including drivers receivers clocking and serialization/deserialization (SerDes) components.Work closely with system architects and RTL designers to define interface requirement

Key ResponsibilitiesDesign and development of analog and mixed-signal circuits for 3D NAND Flash memory supporting array operation peripheral circuitry and power delivery.Drive top-level integration and verification of analog IP within the NAND chip architecture including interaction

Key ResponsibilitiesDesign and development of analog and mixed-signal circuits for 3D NAND Flash memory supporting array operation peripheral circuitry and power delivery.Drive top-level integration and verification of analog IP within the NAND chip architecture including interaction

We are looking for an experienced Senior RTL Design Engineer with deep expertise in front-end and/or back-end digital logic design to help drive the development of next-generation SoC/SSD architectures. This role involves architecture definition RTL design synthesis timing closure and

We are looking for an experienced Senior RTL Design Engineer with deep expertise in front-end and/or back-end digital logic design to help drive the development of next-generation SoC/SSD architectures. This role involves architecture definition RTL design synthesis timing closure and