ASIC RTL Design Engineer
صاحب العمل نشط
حالة تأهب وظيفة
سيتم تحديثك بأحدث تنبيهات الوظائف عبر البريد الإلكتروني
شارك هذه الوظيفة
حالة تأهب وظيفة
سيتم تحديثك بأحدث تنبيهات الوظائف عبر البريد الإلكتروني
الوصف الوظيفي
Responsibilities
- Contribute to the microarchitecture and RTL coding of blocks, function/performance simulation debug, and Lint/CDC/FV/UPF checks.
- Develop SystemVerilog RTL to implement logic for ASIC/SoC products.
- Develop novel ways to automate generation of complex RTL designs.
- Contribute to design methodology, libraries, and code review.
Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
نوع التوظيف
دوام كامل
